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VSC7173 Data Sheet
Enhanced 2:1 Port Selector and 1:2 Port Multiplier for Serial ATA and Serial Attached SCSI
FEATURES
APPLICATIONS

2:1 port selector and 1:2 port multiplier for both Serial ATA (SATA) and Serial Attached SCSI (SAS) links Serial ATA 1.0 compliant at 1.5 Gbps (3.0 Gbps capable) Passes Serial ATA patterns transparently Programmable receiver sensitivity High output swing mode with pre-emphasis Compatible with VSC7175 and VSC7177 designs 0.7 W power dissipation 3.3 V power supply 32-pin, 7 mm x 7 mm QFP-N package
Active-passive redundant failover systems Dual-port Serial ATA and Serial Attached SCSI disk arrays (JBODs) NAS servers RAID subsystems Disk-based backup systems Serial ATA and Serial Attached SCSI routing applications Buffers for externally connected links Serial ATA port replicators Serial ATA Host Bus Adapters selecting between internal and external connectors

To order the VSC7173 device, see "Ordering Information," page 17.
GENERAL DESCRIPTION
The VSC7173 is a Serial ATA and Serial Attached SCSI multiplexer and buffer that implements a 2:1 port selector function for 1.5 Gbps and 3.0 Gbps links. This function is used when dual hosts, such as I/O controllers, must access single-port disk drives in high availability storage subsystems where redundancy and load sharing are important. The outputs from the I/O controllers are multiplexed to a Serial ATA or Serial Attached SCSI drive. The output from the Serial ATA drive is buffered and replicated to the I/O controllers. When switching from one I/O controller to the other, a Serial ATA link must be re-initialized with out-of-band (OOB) signals, which are transferred through the VSC7173 transparently. The VSC7173 provides high output swings with pre-emphasis, and programmable receiver sensitivity that are needed to drive long backplanes and external cables. In addition to the above features, the VSC7173 also supports a 1:2 port multiplier mode where one host can connect two drives. Port connectivity for the device is configured by driving external I/O pins. See the block diagram on page 2.
Maxim Integrated Products
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VSC7173 Data Sheet
VSC7173 Block Diagram
Port 0
P0INP P0INN OOBPORT0 0 P0OUTP P0OUTN En 1S OOB 0 1S
Port 2
P2OUTP En P2OUTN
P2INP OOB P2INN
Port 1
P1INP P1INN OOB
0 P1OUTP P1OUTN En MODE1 1S
Edge-Triggered Logic 0 P0SLTD S1 MODE1 MODE0 PORTSEL0 PORTSEL1 SET RST Q QN
OOBSEL [0:1] HIV [0:2]
I/O Configuration
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VSC7173 Data Sheet
Application Examples
The VSC7173 allows two Serial ATA hosts to access one Serial ATA drive. Figure 1 shows a common application where redundant I/O controllers in disk arrays have multiplexed access to single-port Serial ATA disk drives.
VSC7173 I/O Controller A
I/O Controller B
Serial ATA Drive (1 of n)
Backplane
"Tailgate" Board
Figure 1. Serial ATA Backplane Application Another application example (Figure 2) is for simple port replication to enable an existing Serial ATA Host Bus Adapter (HBA) to connect to two ports. By using the VSC7173, a single channel from the HBA may be selectively connected to an internal connector or an external connector. The VSC7173 provides both the mulitplexing functionality and buffering to drive external connections.
Serial ATA Host Bus Adaptor
Port A
Internal Connector VSC7173 External Connector
PCI Bus Port B
External Connector
Port Multiplier
Figure 2. Port Multiplier Application
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VSC7173 Data Sheet
FUNCTIONAL DESCRIPTIONS
Modes of Operation
Table 1 summarizes the VSC7173 operational mode choices. The mode of the VSC7173 is determined by the following pins. MODE1: Controls whether the selection of port 0 to port 1 is edge-sensitive or level-sensitive. When LOW, port selection is level-sensitive (to enable level-sensitive port selection, pin PORTSEL1 must also be LOW). When HIGH, port selection is edge-sensitive. MODE0: Controls the function of the unselected port. When LOW, the output of this port is turned off. When HIGH, the output of this unselected port is the same data as seen on the selected port. PORTSEL0: In level-sensitive mode (MODE1 is LOW and PORTSEL1 is LOW), controls the selection of port 0 or port 1. When LOW, port 0 is selected; when HIGH, port 1 is selected. In edge-sensitive mode (MODE1 is HIGH), controls the selection of port 0; a rising edge on this pin selects port 0. PORTSEL1: In level-sensitive mode (MODE1 is LOW), must be held LOW. In edge-sensitive mode (MODE1 is HIGH), controls the selection of port 1; a rising edge on this pin selects port 1. Table 1. Port Selection Operating Modes
Input Pins MODE1 0 (level) 0 (level) 0 (level) 0 (level) 1 (edge) 1 (edge) 1 (edge) 1 (edge) MODE0 0 0 1 1 0 0 1 1 PORTSEL0 0 1 0 1 X X PORTSEL1 0 0 0 0 X X P2IN OFF P2IN P2IN OFF P2IN P2IN P2IN High-Speed Connections P0OUT P1OUT OFF P2IN P2IN P2IN P2IN OFF P2IN P2IN P2OUT P0IN P1IN P0IN P1IN P1IN P0IN P1IN P0IN
X = don't care; = rising.
Status Pins
Two output pins, P0SLTD and OOBPORT0, are provided for status monitoring. Table 2 summarizes the functionality of these two output pins. OOBPORT0 reports whether the signal on port 0 is above or below the threshold selected in Table 5. P0SLTD, depending on the state of MODE1, can either report which port is selected or can report whether the signal on port 1 is above or below the threshold selected in Table 5. Table 2. Output Status Pins
Input Pins MODE1 0 (level) PORTSEL0 X PORTSEL1 X P0SLTD OOB status port 1--1 indicates signal is below OOB threshold, 0 indicates signal is above OOB threshold Indicates port selected, 0 = port 1 Indicates port selected, 1 = port 0 Output Status Pins OOBPORT0 OOB status port 0--1 indicates signal is below OOB threshold, 0 indicates signal is above OOB threshold OOB status port 0 OOB status port 0
1 (edge) 1 (edge)
X
X
X = don't care; = rising.
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VSC7173 Data Sheet
Reset State
The power-up state of the VSC7173 is based on the PORTSEL0 and PORTSEL1 input signals. When in levelsensitive mode, the active port connected to port 2 is controlled directly by the PORTSEL0 input. This is the same behavior as the normal operating condition described above. When in edge-sensitive mode, the active port connected to port 2 is defined in Table 3. The state diagram in Figure 3 indicates the same result in a different format.
Table 3. Power-up State (Edge-Sensitive Mode)
PORTSEL0 0 1 0 1 PORTSEL1 0 0 1 1 Active Port Port 0 selected Port 0 selected Port 1 selected Port 0 selected P0SLTD Output 1 1 0 1
Reset=1
Reset State
Reset=1
(PORTSEL0=1, PORTSEL1=1 or PORTSEL1=0) and Reset=0 PORTSEL0
PORTSEL0=0, PORTSEL1=1 and Reset=0
Port 0 Selected
PORTSEL1
Port 1 Selected
Figure 3. Reset State Machine (Edge-Sensitive Mode)
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VSC7173 Data Sheet
High-Speed Outputs
Each port has a high-speed output buffer that transmits the differential serial ATA data at rates up to 3.0 Gbps. The output pins for the ports are P0OUTP/N, P1OUTP/N, and P2OUTP/N. Each output buffer has an input to indicate when OOB signals are being transmitted and a single input to control the output voltage amplitude and to enable preemphasis.
Output Data OutputN
HIV TX Common Mode
Figure 4. High-Speed Output Buffer
Transmitting OOB Signals
Both differential output signals are at the DC-bias voltage when the output buffer is disabled. The output buffer is disabled when OOB signals are transmitted and when an output port is turned "off." For more information, see "Functional Descriptions," page 4.
Output Amplitude and Pre-Emphasis
Each of the output buffers has an amplitude control input pin, the state of which sets the differential output voltage (within normal SATA levels). Pin HIV0 corresponds to port 0, pin HIV1 corresponds to port 1, and pin HIV2 corresponds to port 2. See Table 4. Recommended output AC-coupling capacitor values are 0.01 F. When the amplitude control pin is HIGH, the output is configured for high voltage swing mode, which is useful for driving extended length media such as backplanes or external cables. Setting the output to high swing mode should be done only in controlled environments, because the output voltage exceeds the Serial ATA 1.0 differential mode specifications. The output buffers have a pre-emphasis circuit that is enabled when HIVx is HIGH. Pre-emphasis accentuates higher frequency signals in a transmitted data stream. This feature takes into consideration that a signal loses amplitude and affects the data eye opening as it goes through long trace length runs. Figure 5 shows the effects of the pre-emphasis feature. The amplitude increase is between 20% and 30%, and the duration of the amplitude increase is between 150 ps and 300 ps.
Table 4. Output Amplitude and Pre-Emphasis
HIVx Pin State 0 1 Output Swing Level Normal High Pre-Emphasis None Enabled
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VSC7173 Data Sheet
Pre-Emphasis Disabled
Pre-Emphasis Enabled
VOUT 0 0 1 1 1 1 1 0 1 0
VOUT 0 0 1 1 1 1 1 0 1 0
Figure 5. Pre-Emphasis Diagram
High-Speed Inputs
The high-speed input receivers are designed to achieve Serial ATA 1.0 compliance using AC-coupling as described in the Serial ATA 1.0 specification. Recommended input AC-coupling capacitor values are 0.01 F. The high-speed input receiver contains an OOB signal detector as shown in Figure 6.
Input Receiver Data
Input InputN
OOB Status (OOBPORTx signal) OOBSEL0 OOBSEL1
OOB Detector
Figure 6. High-Speed Input Receiver
OOB Transfer
The VSC7173 cleanly transfers OOB signals from high-speed inputs to outputs. Two status outputs, OOBPORT0 and OOBPORT1, indicate whether the input signal is data or a common-mode state. OOBPORT1 and OOBPORT1 correspond to port 0 and port 1, respectively. An OOB detector monitors the amplitude of an incoming signal in parallel with each high-speed input. When the amplitude is less than the OOB threshold, the OOB status output is driven HIGH. When the incoming amplitude is greater than the OOB threshold, the OOB status output is driven LOW. Setting the OOBSEL1 and OOBSEL0 inputs as shown in the following table configures the OOB threshold level for all three ports. Table 5. Setting the OOB Threshold Level
OOBSEL1 1 0 0 1 OOBSEL0 0 0 1 1 OOB THRESHOLD LEVEL Nominal setting (150 mV to 250 mV) Decrease by ~40 mV Decrease by ~80 mV Increase by ~40 mV
NOTE: All values are differential peak-to-peak voltages.
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VSC7173 Data Sheet
ELECTRICAL SPECIFICATIONS
DC Characteristics
Specifications are guaranteed over the recommended operating conditions listed in Table 11.
Table 6. LVTTL Inputs and Outputs
Symbol VOH VOL VIH VIL II Parameter Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage Input current (includes a weak pull-up resistor) Minimum 2.0 0.0 2.0 0.0 -200 Typical 2.2 0.2 Maximum VDD 0.4 VDD 0.8 +50 Unit V V V V A 0V < VIL < 2.4 V Condition IOH = -4 mA IOL = 4 mA
Table 7. High-Speed Inputs and Outputs
Symbol VTH VOCM Parameter Input threshold voltage for OOB detection High-speed output common-mode voltage Minimum Typical 200 2.0 Maximum Unit mV V Condition See Table 5 on page 7. Normal Swing mode. 100 termination between true and complement outputs. High Swing mode. 100 termination between true and complement outputs.
1.7
V
VICM ZIN
High-speed input common-mode voltage Differential input impedance 85
1.5 100 115
V
Table 8. Power Supply Requirements
Symbol VDD IDD Parameter Power supply voltage Power supply current (total on all supply pins) Total power dissipation Minimum 3.0 Typical 3.3 150 200 540 720 Maximum 3.6 170 235 625 850 Unit V mA mA mW mW Condition 10% on all supplies Normal Swing mode High Swing mode Normal Swing mode High Swing mode
PD
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VSC7173 Data Sheet
AC Characteristics
Specifications are guaranteed over the recommended operating conditions listed in Table 11 on page 11.
High-Speed Input
tON
tOFF
High-Speed Output
Figure 7. Timing Waveform Table 9. High-Speed Inputs and Outputs
Symbol tP tON tOFF tR, tF VOUT(1) Parameter Propagation delay from any high-speed input to high-speed output Propagation delay from signal present at input to output buffer turned on Propagation delay from no signal at input to output buffer turned off Rise and fall times OUTx output differential peak-to-peak voltage swing in normal swing mode (HIVx is LOW) OUTx output differential peak-to-peak voltage swing in high swing mode (HIVx is HIGH) INx input differential peak-to-peak swing with OOBSEL1 = 1 and OOBSEL0 = 0 (OOB nominal) INx input differential peak-to-peak swing with OOBSEL1 = 0 and OOBSEL0 = 1 (OOB minimal) Minimum 0.4 3.0 3.0 67 500 Maximum 2.0 12.0 12.0 260 700 Unit ns ns ns ps mVp-p 1.5 Gbps operation, 20% to 80%. Measured per Serial ATA 1.0 specification, section 6.6.3. 100 termination between true and complement outputs. Measured per Serial ATA 1.0 specification, section 6.6.3. 100 termination between true and complement outputs. Measured per Serial ATA 1.0 specification. Measured per Serial ATA 1.0 specification, section 6.6.3. Condition
VOUT(1, 2)
800
1300
mVp-p
VIN
275
1600
mVp-p
VIN
225
1600
mVp-p
1. Refer to Application Note AN-37 for differential measurement techniques. 2. Output swings are higher than the Serial ATA 1.0 specification to compensate for anticipated PCB or connector losses.
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VSC7173 Data Sheet
tPW PORTSEL0, PORTSEL1
tPW
PORTSEL0 tPSS PORTSEL1 tSW Active Host Port (Port 0 or Port 1) tSW tSW tPSS
* Edge sensitive sideband operation shown in timing diagram.
Note: Edge-sensitive operation shown.
Figure 8. Timing Waveform for Port Switching
Table 10. Port Switch Timing
Symbol tPW tPSS tSW Parameter Pulse width of the port selection pins (PORTSEL0, PORTSEL1). Separation between rising edge transitions of the port selection pins. Switch time. The time required to make the other host port active following an active edge transition of the port selection pins. Minimum 4.0 5.0 5.0 Maximum Unit ns ns ns Edge-sensitive operation Applies to both level and edge-sensitive operations Condition
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VSC7173 Data Sheet
Operating Conditions
Table 11. Recommended Operating Conditions
Symbol VDD T Parameter Power supply voltage Operating temperature(1) Minimum 3.0 0 Typical 3.3 Maximum 3.6 +90 Unit V C
1. Lower limit of specification is ambient temperature, and upper limit is case temperature.
Maximum Ratings
Table 12. Absolute Maximum Ratings
Symbol VDD VINT VOUTT IOT VINS VOUTS IOS TS VESD Parameter Power supply voltage LVTTL input voltage LVTTL output voltage LVTTL output current Serial input voltage Serial output voltage Serial output current Storage temperature Electrostatic voltage discharge, human body model Minimum -0.5 -0.5 -0.5 -50 -0.5 -0.5 -50 -65 -4000 Maximum +4.0 VDD + 0.5 VDD + 0.5 +50 VDD + 0.5 VDD + 0.5 +50 +140 +4000 Unit V V V mA V V mA C V
Stresses listed under Maximum Ratings may be applied to devices one at a time without causing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended periods may affect device reliability.
ELECTROSTATIC DISCHARGE
This device can be damaged by ESD. Maxim recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures may adversely affect reliability of the device.
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VSC7173 Data Sheet
PIN DESCRIPTIONS
The VSC7173 is packaged in a 32-pin, leadless quad flat pack (QFP-N) with an exposed pad.
Pin Diagram
31
29
27
P0SLTD HIV0 P0INP P0INN VSS P0OUTN P0OUTP VDD0
1 23 3
25
RESERVED
P2OUTN
P2OUTP
P2INN
P2INP
VDD2
HIV2
VSS
OOBSEL0 OOBSEL1 VSS
VSC7173 Top View
5
21
MODE1 VDD
19 7 Exposed Die Attach (bottom side)
11 9
PORTSEL0 PORTSEL1
Pad(1) 17
13 15
MODE0
P1INN
HIV1
P1INP
OOBPORT0
VSS
P1OUTP
1. The exposed Die Attach Pad (DAP) is internally connected to ground and should also be connected to VSS on the board.
Figure 9. Pin Diagram
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P1OUTN
VDD1
VSC7173 Data Sheet
Pin Identifications
Table 13. Pin Identifications
Pin Number 7, 6 15, 14 31, 30 3, 4 11, 12 27, 28 19 18 2 10 26 24 23 1 9 Signal P0OUTP, P0OUTN P1OUTP, P1OUTN P2OUTP, P2OUTN P0INP, P0INN P1INP, P1INN P2INP, P2INN PORTSEL0 PORTSEL1 HIV0 HIV1 HIV2 OOBSEL0 OOBSEL1 P0SLTD OOBPORT0 O O LVTTL LVTTL I LVTTL I LVTTL I LVTTL These two inputs select the active port (port 0 or port 1). For more information on the modes of operation, see Table 1 on page 4. When HIGH, these inputs select the high voltage swing output mode for the corresponding output buffer and enable preemphasis. See Table 4 on page 6. These two inputs control the OOB detector threshold voltage for all three input ports. See Table 5 on page 7 for threshold levels. This output reports which port is selected or OOB status of port 1, depending on the value of MODE1. See Table 2 on page 4. When HIGH, this output indicates that the input signal for port 0 is below the OOB threshold. When LOW, the input signal for port 0 is above the OOB threshold. This input is used to select the operating mode for the VSC7173 as described in Table 1 on page 4. This input is used to select the operating mode for the VSC7173 as described in Table 1 on page 4. 3.3 V power supply for all circuits except the high-speed output buffers. 3.3 V output buffer power supply for P0OUTP/N, P1OUTP/N, and P2OUTP/N, respectively. Reserved for future use. Leave unconnected. GND Common ground. DAP is the exposed die attach pad on the bottom of the device. I HighSpeed These are the high-speed differential inputs for port 0, port 1, and port 2. These inputs must be AC-coupled. Type O Level HighSpeed Description These are the high-speed differential outputs for port 0, port 1, and port 2. These outputs must be AC-coupled.
17 21 20 8, 16 32 25 5, 13, 22, 29 DAP
MODE0 MODE1 VDD VDD0, VDD1 VDD2 Reserved VSS
I I
LVTTL LVTTL Power Power
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VSC7173 Data Sheet
PACKAGE INFORMATION
The VSC7173 device is available in a lead(Pb)-free package. VSC7173XYI is a 32-pin leadless quad flat pack (QFP-N) with an exposed pad. Lead(Pb)-free products from Maxim comply with the temperatures and profiles defined in the joint IPC and JEDEC standard IPC/JEDEC J-STD-020. For more information, see the IPC and JEDEC standard.
Thermal Specifications
Thermal specifications for this device are based on the JEDEC standard EIA/JESD51-2 and have been modeled using a four-layer test board with two signal layers, a power plane, and a ground plane (2s2p PCB). For more information, see the JEDEC standard.
Table 14. Thermal Resistances JA (C/W) vs. Airflow (ft/min)
Part Number VSC7173XYI
JC
18.2
0 30.0
100 28.7
200 27.0
To achieve results similar to the modeled thermal resistance measurements, the guidelines for board design described in the JEDEC standard EIA/JESD51 series must be applied. For information about specific applications, see the following: EIA/JESD51-5, Extension of Thermal Test Board Standards for Packages with Direct Thermal Attachment Mechanisms EIA/JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages EIA/JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements EIA/JESD51-10, Test Boards for Through-Hole Perimeter Leaded Package Thermal Measurements EIA/JESD51-11, Test Boards for Through-Hole Area Array Leaded Package Thermal Measurement
Moisture Sensitivity
This device is rated moisture sensitivity level 3 or better as specified in the joint IPC and JEDEC standard IPC/JEDEC J-STD-020. For more information, see the IPC and JEDEC standard.
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VSC7173 Data Sheet
Package Drawing
Bottom View Top View
D 25 24 32 1 1
D2
Exposed Pad Area
0.45 D
17 16 D2 9
8
12 max.
Side View
A
b e A3 A1
L Item A A1 A3 b D D2 e L 0.50 4.95 0.65 BSC 0.75 0.23 7.00 BSC 5.25 Minimum 0.85 nom. 0 0.20 REF 0.35 Maximum 0.90 0.05
NOTES: Drawing not to scale. All units in mm unless otherwise noted. "b" is measured 0.20 to 0.25 from the terminal tip.
Figure 10. Package Drawing
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VSC7173 Data Sheet
Recommended Land Pattern
A A1 D
A2
F
E Vias (16 places)
C
G
Stencil Openings (16 places)
B 7 mm x 7 mm x 0.9 mm Exposed Pad QFP-N 7.445 maximum 5.325 minimum 4.92 maximum 0.37 maximum 1.06 4.95 minimum 5.075 typical 5.20 maximum E F G 5.10 1.0 1.2 Solder mask opening dimension Stencil opening dimensions Stencil opening and via spacing Thermal land dimensions
Land Pad Detail
Item A A1 A2 B C D
Comments
NOTES: All vias 0.30 to 0.33 diameter, plugged. Drawing not to scale. All dimensions are in mm unless otherwise noted.
Figure 11. Recommended Land Pattern
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VSC7173 Data Sheet
ORDERING INFORMATION
The VSC7173 device is available in a lead(Pb)-free package. VSC7173XYI is 32-pin leadless quad flat pack (QFP-N) with an exposed pad. Lead(Pb)-free products from Maxim comply with the temperatures and profiles defined in the joint IPC and JEDEC standard IPC/JEDEC J-STD-020. For more information, see the IPC and JEDEC standard.
Table 15. VSC7173 Ordering Information
Part Number VSC7173XYI Description Lead(Pb)-free 32-pin QFP-N, 7 mm x 7 mm x 0.9 mm body
Maxim Integrated Products 120 San Gabriel Drive Sunnyvale, CA 94086 United States
408-737-7600 www.maxim-ic.com
Copyright (c) 2004 to 2005 Maxim Integrated Products Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. Maxim retains the right to make changes to its products or specifications to improve performance, reliability or manufacturability. All information in this document, including descriptions of features, functions, performance, technical specifications and availability, is subject to change without notice at any time. While the information furnished herein is held to be accurate and reliable, no responsibility will be assumed by Maxim for its use. Furthermore, the information contained herein does not convey to the purchaser of microelectronic devices any license under the patent right of any manufacturer. Maxim products are not intended for use in life support products where failure of a Maxim product could reasonably be expected to result in death or personal injury. Anyone using a Maxim product in such an application without express written consent of an officer of Maxim does so at their own risk, and agrees to fully indemnify Maxim for any damages that may result from such use or sale. is a registered trademark of Maxim Integrated Products, Inc. All other products or service names used in this publication are for identification purposes only, and may be trademarks or registered trademarks of their respective companies. All other trademarks or registered trademarks mentioned herein are the property of their respective holders.
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